The recent trend of miniaturizing sophisticated electronic devices has led to a corresponding increase in the demand for improved packaging density of the semiconductor devices mounted on the electronic device. A popular technique for improving packaging density is a stack type semiconductor device produced through chip-on-chip technology and package-on-package technology.
Japanese Unexamined Patent Application Publication No. 2005-11856 discloses a semiconductor device which allows vertical electric coupling by burying a through hole formed in a pseudo wafer for fixing a semiconductor chip with a conductive resin. Japanese Unexamined Patent Application Publication No. 2003-218283 discloses a semiconductor device with a protruding electrode formed on a substrate mounted with a semiconductor chip for establishing a vertical electric coupling.
A stack type semiconductor device requires a connector terminal to be formed for electrically coupling with other semiconductor chips or the semiconductor package when stacking. Conventionally, an additional manufacturing step is required for forming the connector terminal (for example, formation of a through hole and a through electrode). Accordingly, with the addition of the step for forming the connector terminal, improving the fabrication yield to reduce manufacturing costs is difficult to achieve.